A copending United States patent application Ser. No. 53,497 of Miersch and Romankiw, entitled "Thin Film Metal Package for LSI Chips" (YO978-065) describes a chip packaging carrier wherein several parallel power conducting carrier plates are stacked parallel to the surface upon which the chip terminals are connected electrically to pads. The planes are extensive in area and dielectric material is present in the spaces between the plates. Thus, high capacitance is afforded by such a structure. However, it is complicated to supply a large number of connections from the plates to the chips because numerous connections must be made through the parallel plates of metal up to the connection pads on the top surface of the packaging carrier.
U.S. Pat. No. 3,562,592 teaches placing chips at 45.degree. relative to thin film conductor tracks, as distinguished from conductor carrier plates.
An object of this invention is to provide an efficient packaging structure for VLSI chips in high density applications wherein electrical noise from simultaneous switching of a large number of circuits must be suppressed as much as possible by providing high capacitance between power supply conductors to the chips as close as possible to the chips, and several power supply conductors must be connected to each chip.
Another object of this invention is to provide a simple, manufacturable and practical packaging structure which inhibits noise in high speed computers .